|
For using the library, all test_*.vhdl files must be compiled under a
library named "Test". These file must be added to the current files
of the project to test.
The design which is to benefits from VhdlTestIt! library must be in
structural abstraction (gate level design), which specifically, it
must only use and, nand, or, nor, inv, xor, xnor, dff entities in the
design.
Modifications to the Circuit Under Test (CUT)
- Library Statements:
At the beginning of the code, Test library should be used in addition to its Tools and test_logic packages.
- Gate Components:
Original primitive gates used in the
design must be changed to the corresponding gates in the
library. This can be accomplished by means of simple
component declarations, in the declaration part of the
architecture. Gate components declared in the library are: INVG, ORG_N, NORG_N, ANDG_N, NANDG_N, XORG_N, DFF which
corresponds to not gate, n-input or, nor, and, nand, xor gates and d-flipflops. Exact declarations can be found in test_tools.vhdl.
- Internal Signals:
All of internal signals must be changed to test_ulogic and test_ulogic_vector's. Inputs and outputs of the CUT are remained
untouched. They will be converted to suitable signal types
by means of PI and PO components.
- Input and Output Ports:
All of the input signals must be
aggregated into a big std_ulogic_vector. This can simply be
done by defining a big vector in input or output, then
assigning its items to their actual signals which is now
defined in the declaration part of the architecture.
In sequential circuits a third signal of type std_ulogic must
be used which is the data clock of the network.
- Primary Inputs and Outputs:
All inputs and outputs must be
passed through two special gates, namely, PI_N and PO_N gates. Therefore it is necessary to declare two vector signals
exactly with the same size of primary input and primary output
say, inp and outp. The input of PI_N is primary input and its
output is inp. The input of PO_N is outp and its output is
primary output.
- Fanouts:
It is an optional step and also the most time
consuming one which is needed for fault collapsing algorithm
to work. If the complete fault list generation and the more
time needed for test generation can be tolerated, it is not
necessary to insert fan-out gates. All of the signals
which are inputs to at least two gates must be considered as
a fan-out and a unique FOUT_N must be inserted in the place
of fan-out. The input of FOUT_N is the signal but a new
signal must be declared with the size of fan-outs (e.g. 3 if
the signal is input to 3 gates) and the output of FOUT_N is
this new signal. Also input of those gates must be changed to
items of this newly declared signal.
A new VHDL code is needed as the top level entry which instantiates a
TestSystem. In the configurable TestSystem (provided by the library)
a CUT must be configured as the under test circuit which is connected
to a test equipment configurable to be fault simulation, fault collapsing
or test generation.
Services Provided by VhdlTestIt! |
|
The following services are provided currently by the VhdlTestIt! in its
TestSystem.
1. Gatelist Generation
A list of all gates is generated automatically when all of the
gates are instantiated in the design and is exported to a text
file (default: gatelist.txt) using GatelistExport procedure.
2. Linelist Generation
A list of all lines (internal signals) is generated automatically
when all of the gates are instantiated in the design and is
exported to a text file (default: linelist.txt) using LinelistExport procedure.
3. Faultlist Generation
Two methods are provided using FaultlistExport procedure to
generate faults in the circuit. The method can be selected by changing
FC_TYPE constant in test_tools.vhdl. First method, NORMAL, is a complete
fault list generation. It considers all inputs and outputs of gates
and in each line, both sa-0 and sa-1. Second method, LINE_ORIENTED,
uses a method named line-oriented that considers just inputs of gates and
according to the gate type, just sa-0 or just sa-1 or both sa-0 and
sa-1 are inserted into the fault list. All of the possible faults
are also automatically export to a text file (default: faultlist.txt)
by FaultlistExport.
4. Fault Simulation
An entity/architecture named FaultSimulator is implemented in
test_benchs.vhdl which must instantiated inside TestSystem. It connects
to the design under test by applying primary
inputs, primary outputs and data clock of the design to this
architecture in a testbench. This architecture accepts an input file
name via a generic parameter that contains the test vectors to
apply. Each line of the file must contain a test vector with the size
of primary input in binary format. The architecture also accepts
another file name via another generic parameter that denotes the
result of fault simulation. This file contains the golden response of
each test vector in addition to the faults that it detects (with
their faulty different responses from golden response). Faults are
removed from active fault list when moving on next test vector.
Fault simulation for sequential circuits are carried out depending
on the format of the input file. If a test vector of the input file
contains only the number of bits equals to number of primary input
bits, fault simulation is executed by applying this test vector,
clocking the circuit, observe the response and save the state of
flip-flops for next test vector application. If the number of bits
in an input test vector equals to the number of primary input
bits plus number of flip-flops, then the full scan method is used.
This is the vector is broken to its consisting parts, the primary
input applies, the scan register fills with input scan vector,
then the circuit is clocked and primary output in addition to
output scan vector (contents of flip-flops after clocking) is
observed.
If fault simulation is activated at TestSystem, by default the file test_in.txt is used as the input and test_fs_out.txt as the output.
5. Random Test Generation
An entity/architecture named TestGeneration is implemented in
test_benchs.vhdl which must instantiated inside TestSystem. Its
connects completely to the design under test by applying primary
inputs, primary outputs and data clock of the design to this
architecture in a testbench. This architecture accepts two output
file names via a generic parameter. First one would contain the
only generated test vectors, while the second one not only fills with
the generated test vectors, but also with the full description about
each test vector generated; including its golden response, faults
that it detects and their corresponding faulty outputs. Currently, a
pure random test generation method is used in this architecture.
Test generation for sequential circuits are implemented using two
methods: first, only test vectors for primary input is considered
and the state of the circuit must be preserved for next text vector.
Second, a full scan method is assumed to be applied to the circuit.
It means that a generated test vector, contains a part for primary
input in addition to another part for scan register.
Random test generation can be configured to continue until a desired
fault coverage is reached. The desired fault coverage can be changed
by modifying MAX_RATIO constant in test_tools.vhdl. Also a parameter
is defined to terminate (give up) the test generation process after a
number of unsuccessful tries. These parameters are defined by means of
some constants in the package Tools (test_tools.vhdl).
If test generation is activated at TestSystem, by default the file tg_out.txt is used as the output of detail generation andtg_raw.txt as the output of just the produced test vectors.
As an example, assume the CUT is c17.vhdl. The file is first processed using V2S to insert fan-outs. Then the required modifications described before are applied. This new file my_c17.vhdl is then added to a project having the VhdlTestIt! library. The whole project is compiled, tester_c17 is simulated and thus the results are produced.
| The original CUT, c17.vhdl is:
library IEEE;
use IEEE.std_logic_1164.all;
library selfext;
use work.gates_pkg.all;
use work.fflop_pkg.all;
ENTITY c17_i89 IS
PORT (
INP: in std_ulogic_vector(0 to 4);
OUTP : out std_ulogic_vector(0 to 1);
H : in std_ulogic
);
END c17_i89 ;
ARCHITECTURE structural OF c17_i89 IS
signal INTERP : std_ulogic_vector(0 to 3):=(others=>'0') ;
signal OUTPI : std_ulogic_vector(OUTP'range):=(others=>'0') ;
BEGIN
NAND0 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(0),
inp(1) => INP(2),
out1 => INTERP(0));
NAND1 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(2),
inp(1) => INP(3),
out1 => INTERP(1));
NAND2 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(1),
inp(1) => INTERP(1),
out1 => INTERP(2));
NAND3 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(1),
inp(1) => INP(4),
out1 => INTERP(3));
NAND4 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(0),
inp(1) => INTERP(2),
out1 => OUTPI(0));
NAND5 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(2),
inp(1) => INTERP(3),
out1 => OUTPI(1));
BUFFER_OUT : OUTP <= OUTPI;
END structural ;
|
After fanout insertion and modifications, my_c17.vhdl will be:
library IEEE;
use IEEE.std_logic_1164.all;
LIBRARY Test;
USE Test.Tools.ALL;
USE Test.test_logic.ALL;
ENTITY c17_i89 IS
PORT (
INP_PI: in std_ulogic_vector(0 to 4);
OUTP_PO : out std_ulogic_vector(0 to 1);
H : in std_ulogic
);
END c17_i89 ;
ARCHITECTURE structural OF c17_i89 IS
signal INTERP : test_ulogic_vector(0 to 3):=(others=>test_ulogic_init);
signal OUTPI : test_ulogic_vector(OUTP'range):=(others=>test_ulogic_init);
--------------------
-- fanout signals
signal INP_2 : test_ulogic_vector(1 to 2);
signal INTERP_1 : test_ulogic_vector(1 to 2);
signal INTERP_2 : test_ulogic_vector(1 to 2);
-- Primary Input Signals
SIGNAL INP : test_ulogic_vector(INP_PI'RANGE);
SIGNAL OUTP : test_ulogic_vector(OUTP_PO'RANGE);
BEGIN
-- PIs
PI0 : PI_N port map (i => INP_PI, o => INP);
-- POs
PO0 : PO_N port map (i => PUTP, o => OUTP_PO);
--------------------
-- fanout components
FO0 : FOUT_N generic map (2)
port map (INP(2), INP_2);
FO1 : FOUT_N generic map (2)
port map (INTERP(1), INTERP_1);
FO2 : FOUT_N generic map (2)
port map (INTERP(2), INTERP_2);
NAND0 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(0),
inp(1) => INP_2 (1),
out1 => INTERP(0));
NAND1 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP_2 (2),
inp(1) => INP(3),
out1 => INTERP(1));
NAND2 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(1),
inp(1) => INTERP_1 (1),
out1 => INTERP(2));
NAND3 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP_1 (2),
inp(1) => INP(4),
out1 => INTERP(3));
NAND4 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(0),
inp(1) => INTERP_2 (1),
out1 => OUTPI(0));
NAND5 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP_2 (2),
inp(1) => INTERP(3),
out1 => OUTPI(1));
BUFFER_OUT : OUTP <= OUTPI;
END structural ; |
List of all gates, gatelist.txt:
# A tab seperated list of gates:
#id path_name gate_type in_no out_no
1 :testbench:ts:cut:nand5:core: g_nand 2 1
2 :testbench:ts:cut:nand4:core: g_nand 2 1
3 :testbench:ts:cut:nand3:core: g_nand 2 1
4 :testbench:ts:cut:nand2:core: g_nand 2 1
5 :testbench:ts:cut:nand1:core: g_nand 2 1
6 :testbench:ts:cut:nand0:core: g_nand 2 1
7 :testbench:ts:cut:fo2:core: g_fout 1 2
8 :testbench:ts:cut:fo1:core: g_fout 1 2
9 :testbench:ts:cut:fo0:core: g_fout 1 2
10 :testbench:ts:cut:po0:core: g_po 2 2
11 :testbench:ts:cut:pi0:core: g_pi 5 5
|
List of all lines (signals), linelist.txt:
# A tab seperated list of lines:
#id level from_gate [from_pin] to_gate [to_pin]
1 8 1 [1] 10 [2]
2 8 2 [1] 10 [1]
3 6 3 [1] 1 [2]
4 6 4 [1] 7 [1]
5 4 5 [1] 8 [1]
6 4 6 [1] 2 [1]
7 7 7 [1] 2 [2]
8 7 7 [2] 1 [1]
9 5 8 [1] 4 [2]
10 5 8 [2] 3 [1]
11 3 9 [1] 6 [2]
12 3 9 [2] 5 [1]
13 9 10 [1] 0 [0]
14 9 10 [2] 0 [0]
15 2 11 [1] 6 [1]
16 2 11 [2] 4 [1]
17 2 11 [3] 9 [1]
18 2 11 [4] 5 [2]
19 2 11 [5] 3 [2]
20 1 0 [0] 11 [1]
21 1 0 [0] 11 [2]
22 1 0 [0] 11 [3]
23 1 0 [0] 11 [4]
24 1 0 [0] 11 [5]
|
List of all faults collapsed by LINE_ORIENTED method, faultlist.txt:
# A tab seperated list of faults:
#id line_no sa_value to_gate [to_pin]
1 15 1 6 [1]
2 16 1 4 [1]
3 17 0 9 [1]
4 17 1 9 [1]
5 18 1 5 [2]
6 19 1 3 [2]
7 11 1 6 [2]
8 12 1 5 [1]
9 6 1 2 [1]
10 5 0 8 [1]
11 5 1 8 [1]
12 9 1 4 [2]
13 10 1 3 [1]
14 4 0 7 [1]
15 4 1 7 [1]
16 3 1 1 [2]
17 7 1 2 [2]
18 8 1 1 [1]
19 2 0 10 [1]
20 2 1 10 [1]
21 1 0 10 [2]
22 1 1 10 [2]
|
Generated test patterns (fault coverage: 100%), tg_raw.txt:
#************************************************************
# Fault Coverage: 22 / 22 = .10000
# # of test vectors: 4
# # value changes: 0
01010
11111
00101
10000
|
| Details of random test generation process, tg_out.txt: |
Test Vector: 01010
Golden Response: 11
F4 Response: 00
F8 Response: 00
F10 Response: 00
F15 Response: 00
F17 Response: 01
F18 Response: 10
F19 Response: 01
F21 Response: 10
------------------------------------------------------------
Test Vector: 11111
Golden Response: 10
F3 Response: 11
F9 Response: 00
F11 Response: 11
F12 Response: 11
F13 Response: 11
F14 Response: 11
F22 Response: 11
|
------------------------------------------------------------
Test Vector: 00101
Golden Response: 01
F1 Response: 11
F2 Response: 11
F5 Response: 00
F16 Response: 00
F20 Response: 11
------------------------------------------------------------
Test Vector: 10000
Golden Response: 00
F6 Response: 01
F7 Response: 10
************************************************************
Fault Coverage: 22 / 22 = .10000
# of test vectors: 4
# value changes: 0
|
ModelSim Compilation of VhdlTestIt! |
ModelSim Simulation of VhdlTestIt! |
ModelSim Waveform of VhdlTestIt! |
|
VhdlTestIt!
