| As an example in VHDL, assume c17.vhdl:
library IEEE;
use IEEE.std_logic_1164.all;
library selfext;
use work.gates_pkg.all;
use work.fflop_pkg.all;
ENTITY c17_i89 IS
PORT (
INP: in std_ulogic_vector(0 to 4);
OUTP : out std_ulogic_vector(0 to 1);
H : in std_ulogic
);
END c17_i89 ;
ARCHITECTURE structural OF c17_i89 IS
signal INTERP : std_ulogic_vector(0 to 3):=(others=>'0') ;
signal OUTPI : std_ulogic_vector(OUTP'range):=(others=>'0') ;
BEGIN
NAND0 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(0),
inp(1) => INP(2),
out1 => INTERP(0));
NAND1 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(2),
inp(1) => INP(3),
out1 => INTERP(1));
NAND2 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(1),
inp(1) => INTERP(1),
out1 => INTERP(2));
NAND3 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(1),
inp(1) => INP(4),
out1 => INTERP(3));
NAND4 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(0),
inp(1) => INTERP(2),
out1 => OUTPI(0));
NAND5 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(2),
inp(1) => INTERP(3),
out1 => OUTPI(1));
BUFFER_OUT : OUTP <= OUTPI;
END structural ; |
After processing c17_fo.vhdl will be:
library IEEE;
use IEEE.std_logic_1164.all;
library selfext;
use work.gates_pkg.all;
use work.fflop_pkg.all;
ENTITY c17_i89 IS
PORT (
INP: in std_ulogic_vector(0 to 4);
OUTP : out std_ulogic_vector(0 to 1);
H : in std_ulogic
);
END c17_i89 ;
ARCHITECTURE structural OF c17_i89 IS
signal INTERP : std_ulogic_vector(0 to 3):=(others=>'0') ;
signal OUTPI : std_ulogic_vector(OUTP'range):=(others=>'0') ;
--------------------
-- fanout signals
signal INP_2 : std_ulogic_vector(1 to 2);
signal INTERP_1 : std_ulogic_vector(1 to 2);
signal INTERP_2 : std_ulogic_vector(1 to 2);
BEGIN
--------------------
-- fanout components
FO0 : FOUT_N generic map (2)
port map (INP(2), INP_2);
FO1 : FOUT_N generic map (2)
port map (INTERP(1), INTERP_1);
FO2 : FOUT_N generic map (2)
port map (INTERP(2), INTERP_2);
NAND0 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(0),
inp(1) => INP_2 (1),
out1 => INTERP(0));
NAND1 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP_2 (2),
inp(1) => INP(3),
out1 => INTERP(1));
NAND2 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(1),
inp(1) => INTERP_1 (1),
out1 => INTERP(2));
NAND3 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP_1 (2),
inp(1) => INP(4),
out1 => INTERP(3));
NAND4 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(0),
inp(1) => INTERP_2 (1),
out1 => OUTPI(0));
NAND5 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP_2 (2),
inp(1) => INTERP(3),
out1 => OUTPI(1));
BUFFER_OUT : OUTP <= OUTPI;
END structural ; |
| And as an example in Verilog, assume c17.v:
module c17 (N1,N2,N3,N6,N7,N22,N23);
input N1,N2,N3,N6,N7;
output N22,N23;
wire N10,N11,N16,N19;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
nand NAND2_4 (N19, N11, N7);
nand NAND2_5 (N22, N10, N16);
nand NAND2_6 (N23, N16, N19);
endmodule
|
After processing c17_fo.v will be:
module c17_fo (N1_PI,N2_PI,N3_PI,N6_PI,N7_PI,N22_PO,N23_PO);
input N1_PI,N2_PI,N3_PI,N6_PI,N7_PI;
output N22_PO,N23_PO;
wire N10,N11,N16,N19;
// New Introduced Signals (inputs/outputs)
wire N1, N2, N3, N6, N7, N22, N23;
// New Introduced Signals (fanouts)
wire N3_0, N3_1,
N11_0, N11_1,
N16_0, N16_1;
// New Primary Input (PI) components
pi pi_0 (N1_PI, N1);
pi pi_1 (N2_PI, N2);
pi pi_2 (N3_PI, N3);
pi pi_3 (N6_PI, N6);
pi pi_4 (N7_PI, N7);
// New Primary Output (PO) components
po po_0 (N22, N22_PO);
po po_1 (N23, N23_PO);
// New Fan-out (FANOUT) components
fanout_n #(2,0,0) fanout_n_0 (N3, {N3_0, N3_1});
fanout_n #(2,0,0) fanout_n_1 (N11, {N11_0, N11_1});
fanout_n #(2,0,0) fanout_n_2 (N16, {N16_0, N16_1});
nand_n #(2,0,0) NAND2_1 (N10, {N1, N3_0});
nand_n #(2,0,0) NAND2_2 (N11, {N3_1, N6});
nand_n #(2,0,0) NAND2_3 (N16, {N2, N11_0});
nand_n #(2,0,0) NAND2_4 (N19, {N11_1, N7});
nand_n #(2,0,0) NAND2_5 (N22, {N10, N16_0});
nand_n #(2,0,0) NAND2_6 (N23, {N16_1, N19});
endmodule
|
The main window of the V2S is an editor of source code. New code can be written from scratch, opened, or copy/pasted into. To open a Verilog or VHDL file in use File -> Open... The application stores four recent files for quick access. When a file is opened, the type is guessed from its extension, i.e. ".v" for Verilog, ".vhd" and ".vhdl" for VHDL. In case the type is not determined correctly, use Tools -> HDL Language to specify it.
File Menu |
Tools Menu |
The tools menu also has Tools -> Code Properties item to inspect source code from syntactical and semantical point of view. In its report window the report of tokenizer, parser and processor will be found. Details of data structures and outputs of each processing unit are listed completely. Basic editing facilities and their popular shortcuts have been provided accessible by Edit menu. Undo/redo has a command list in order to make it possible an arbitrary number of step backwards and step forwards.
Report (VHDL) |
Edit Menu |
To insert fanouts in a Verilog file, the following dialog appears after selecting the Tools -> Insert Fanouts... . Output file name will be generated automatically. Optional comments and declarations can be inserted at the beginning of the output file. Some signals and modules can be ignored completely from the processing declared at "Ignore Entities" section. The naming pattern of new components (fanout, PI and PO) can be specified in addition to an excessive data for how an existing module (such as "nand") will be modified. All of the editable regions has context help to assist the user. When the fanout insertion completed successfully, it is possible to view the produced code in a seperate window and to observe the differences from the original code.
Verilog Fanout Insersion Dialog |
Result (Verilog) |
To insert fanouts in a VHDL file, the following dialog appears after selecting the Tools -> Insert Fanouts... . Output file name will be generated automatically. List of input signal names of gates can be specified in this dialog. Note that all of the settings of this dialog and the one for Verilog will be stored appropriately (e.g., registery in Windows and .ini files in Linux) for later retreival. Also the default options can be called using "Restore Defaults" button. The produced code can be viewed in a seperate window after the insertion is done, like before.
VHDL Fanout Insersion Dialog |
Result (VHDL) |
|
V2S
